`include "constant.svh"

module Process(
	input clk,
	input rst,
	input [7:0] data,
	input ready,
	input overflow,
	output reg nextdata_n,
	output reg key, 		// 1:press 0: release
	output [7:0] ascii
);
	reg flag; // whether code is break code
	
	always @(posedge clk) begin
		if(rst) begin
			flag <= 0;
		end else begin
			if(ready) begin
				if(data == `BREAKCODE) begin
					flag <= 1;
				end else begin
					if(flag) begin
						key <= 0;
						flag <= 0;
					end else begin
						key <= 1;
					end
				end
				nextdata_n <= ~nextdata_n;
			end else begin
				nextdata_n <= 0;
			end
		end
	end

	mux mux(
		.data(data),
		.ascii(ascii)
	);



endmodule
